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AL422 data sheets (revision v1. 1)
AL422 AL422b january 23, 2001 2 amendments (since april 2, 1999) 05 - 13 - 99 dc/ac characteristics (including current consumption) updated. 07 - 02 - 99 pinout diagram (5.0) and dc external load (7.4) modified. 08 - 03 - 99 description about tst pin added in sections 6.0 & 8.1. 09 - 02 - 99 8.3.2 rewritten. 10 - 26 - 99 capacitance provided in the ac characteristics section. 1 2 - 15 - 99 remove tst pin restriction. 01 - 18 - 01 1. revised section ?8.3.2 read enable during reset cycles? to ?8.3.2 the proper m anipulation of fifo access?. 2. add section ?8.3.3 single field write with multiple read operation? 3. add section ?8.3.4 one field delay line (the old data read)?
AL422 AL422b january 23, 2001 3 AL422 3m - bits fifo field memory contents: 1.0 description ________________________________ ________________________________ 4 2.0 features ________________________________ ________________________________ ___ 4 3.0 applications ________________________________ ________________________________ 4 4.0 ordering information ________________________________ ________________________ 4 5.0 pinout diagram ________________________________ ____________________________ 5 6.0 pin description ________________________________ _____________________________ 5 7.0 electrical characteristics ________________________________ _____________________ 6 7.1 absolute maximum ratings ________________________________ ________________________ 6 7.2 recommended operating conditions ________________________________ ________________ 6 7.3 dc characteristics ________________________________ _______________________________ 6 7.4 ac characteristics ________________________________ _______________________________ 7 7.5 timing diagrams ________________________________ ________________________________ _ 9 8.0 functional description ________________________________ ______________________ 13 8.1 memory operation ________________________________ ______________________________ 14 8.2 5v and 3.3v applica tions ________________________________ _________________________ 15 8.3 application notes ________________________________ _______________________________ 16 8.3.1 irregular read/write ________________________________ ________________________________ _ 16 8.3.2 the proper manipulation of fifo access ________________________________ _________________ 17 8.3.3 single field write with multiple read operation ________________________________ ___________ 17 8.3.4 one field delay line (the old data read) ________________________________ _______________ 17 9.0 mechanical drawing ________________________________ _______________________ 19
AL422 AL422b january 23, 2001 4 1.0 description the AL422 consists of 3m - bits of dra m, and is configured as 393,216 words x 8 bit fifo (first in first out). the interface is very user - friendly since all complicated dram operations are already managed by the internal dram controller. current sources of similar memory (field memory) in the market provide limited memory size which is only enough for holding one tv field, but not enough to hold a whole pc video frame which normally contains 640x480 or 720x480 bytes. the averlogic AL422 provides 50% more memory to support high resolution for digital pc graphics or video applications. the 50% increase in speed also expands the range of applications. 2.0 features 384k (393,216) x 8 bits fifo organization support vga, ccir, ntsc, pal and hdtv resolutions independent read/write operations (di fferent i/o data rates acceptable) high speed asynchronous serial access read/write cycle time: 20ns access time: 15ns output enable control (data skipping) self refresh 5v or 3.3v power supply standard 28 - pin sop package 3.0 applications multimedia syste ms video capture systems video editing systems scan rate converters tv?s picture in picture feature time base correction (tbc) frame synchronizer digital video camera buffer for communications systems 4.0 ordering information part number package p ower supply status AL422b 28 - pin plastic sop +5/+3.3 volt shipping AL422v5 28 - pin plastic sop +5 volt replaced by AL422b AL422v3 28 - pin plastic sop +3.3 volt replaced by AL422b
AL422 AL422b january 23, 2001 5 5.0 pinout diagram 6.0 pin description pin name pin # i/o type fu nction di0~di7 1~4, 11~14 input data input wck 9 input write clock /we 5 input (active low) write enable /wrst 8 input (active low) write reset do0~do7 15~18, 25~28 output (tristate) data output rck 20 input read clock /re 24 input (active low) read enable /rrst 21 input (active low) read reset /oe 22 input (active low) output enable tst 7 input test pin (pulled - down)* vdd 10 5v or 3.3v dec/vdd 19 decoupling cap input gnd 6, 23 ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 di0 di1 di2 di3 /we gnd tst /wrst wck vdd di4 di5 di6 di7 do0 do1 do2 do3 /re gnd /oe /rrst rck dec do4 do5 do6 do7 AL422-04 422b pinout diagram averlogic AL422b xxxxx xxxx lot number date code
AL422 AL422b january 23, 2001 6 7.0 electrical characteristics 7.1 absolute maximum r atings ratings parameter 3.3v application 5v application unit v dd supply voltage - 1.0 ~ +4.5 - 1.0 ~ +7.0 v v p pin voltage - 1.0 ~ +5.5 - 1.0 ~ v dd +0.5 v i o output current - 20 ~ +20 - 20 ~ +20 ma t amb ambient op. temperature 0 ~ +70 0 ~ +70 c t stg s torage temperature - 55 ~ +125 - 55 ~ +125 c 7.2 recommended operating conditions 3.3v application 5v application parameter min max min max unit v dd supply voltage +3.0 +3.6 +4.5 +5.25 v v ih high level input voltage +2.0 +5.5 +3.0 v dd +0.5 v v il lo w level input voltage - 1.0 +0.8 - 1.0 +0.8 v 7.3 dc characteristics ( v dd =5v or 3.3v, vss=0v. t amb = 0 to 70c) 3.3v application 5v application parameter min typ max min typ max unit i dd operating current @20mhz - 33 - - 50 - ma i dd operating curre nt @30mhz - 45 - - 66 - ma i dd operating current @40mhz - 57 - - 82 - ma i dd operating current @50mhz - 68 - - 97 - ma i dds standby current - 7 - - 12 - ma v oh hi - level output voltage 0.7v dd - v dd +3.0 - v dd v v ol lo - level output voltage - - +0.4 - - +0.4 v i li input leakage current - 10 - +10 - 10 - +10 m a i lo output leakage current - 10 - +10 - 10 - +10 m a
AL422 AL422b january 23, 2001 7 7.4 ac characteristics ( v dd =5v or 3.3v, vss=0v, t amb = 0 to 70c) 3.3v application 5v application parameter min max min max unit t wc wck cycle time 20 1000 20 1000 ns t wph wck high pulse width 7 - 7 - ns t wpl wck low pulse width 7 - 7 - ns t rc rck cycle time 20 1000 20 1000 ns t rph rck high pulse width 7 - 7 - ns t rpl rck low pulse width 7 - 7 - ns t ac access time - 15 - 15 ns t oh outpu t hold time 4 - 4 - ns t hz output high - z setup time 3 15 4 15 ns t lz output low - z setup time 3 15 4 15 ns t wrs /wrst setup time 5 - 6 - ns t wrh /wrst hold time 2 - 3 - ns t rrs /rrst setup time 5 - 6 - ns t rrh /rrst hold time 2 - 3 - ns t ds input dat a setup time 5 - 6 - ns t dh input data hold time 2 - 3 - ns t wes /we setup time 5 - 6 - ns t weh /we hold time 2 - 3 - ns t wpw /we pulse width 10 - 10 - ns t res /re setup time 5 - 6 - ns t reh /re hold time 2 - 3 - ns t rpw /re pulse width 10 - 10 - ns t oes /oe setup time 5 - 6 - ns t oeh /oe hold time 2 - 3 - ns t opw /oe pulse width 10 - 10 - ns t tr transition time 2 20 3 20 ns c i input capacitance - 7 - 7 pf c o output capacitance - 7 - 7 pf
AL422 AL422b january 23, 2001 8 input voltage levels are defined as vih=3.0v and vil=0 .4v. the read address needs to be at least 128 cycles after the write address. do external load:
AL422 AL422b january 23, 2001 9 7.5 timing diagrams cycle n reset cycle (s) cycle 0 cycle 1 wck /wrst di7~0 AL422-05 write cycle timing (write reset) t tr t wrs t wrh n-1 n 0 1 t ds t dh /we = "l" rck /rrst do7~0 n-1 n t oh AL422-07 read cycle timing (read reset) t rph t rpl 0 1 cycle n reset cycle (s) cycle 0 cycle 1 t rrs t rrh t ac 0 /re = /oe = "l"
AL422 AL422b january 23, 2001 10 cycle n cycle n+1 cycle n+3 rck /oe do7~0 n-1 n AL422-09 read cycle timing (output enable) t rph t rpl t oes t oeh t rc n+1 t opw t oh t ac cycle n+2 hi-z cycle n+4 n+4 t hz t lz /re = "l" cycle n cycle n+1 disable cycle (s) rck /re do7~0 n-1 n AL422-08 read cycle timing (read enable) t rph t rpl t res t reh t rc n+1 t rpw t oh t ac n+2 cycle n+2 /oe = "l"
AL422 AL422b january 23, 2001 11 cycle n cycle n+1 disable cycle (s) wck /we di7~0 n-1 n t ds t dh AL422-06 write cycle timing (write enable) t wph t wpl t wes t weh t wc n+1 n+2 t wpw cycle n+2 cycle n cycle n+1 disable cycle (s) rck /re do7~0 n-1 n AL422-14 read cycle timing (re, rrst) t rph t rpl t res t reh t rc n+1 t rpw t oh t ac 0 t rrs t rrh /rrst cycle 0 /oe = "l"
AL422 AL422b january 23, 2001 12 cycle n cycle n+1 disable cycle (s) wck /we di7~0 n-1 n t ds t dh AL422-15 write cycle timing (we, wrst) t wph t wpl t wes t weh t wc n+1 1 t wpw cycle 0 t wrs t wrh /wrst 0 cycle 1
AL422 AL422b january 23, 2001 13 8.0 functional description the AL422 is a video frame buffer consisting of dram that works lik e a fifo which is long enough to hold up to 819x480 bytes of picture information and fast enough to operate at 50mhz. the functional block diagram is as follows: the i/o pinouts and functions are described as follows: di7~di0 data input : data is input on the rising edge of the cycle of wck when /we is pulled low (enabled). do7~do0 data output: data output is synchronized with the rck clock. data is obtained at the rising edge of the rck clock when /re is pulled low. the access time is defined from the r ising edge of the rck cycle. wck write clock input: the write data input is synchronized with this clock. write data is input at the rising edge of the wck cycle when /we is pulled low (enabled). the internal write address pointer is incremented automatic ally with this clock input. rck read clock input: the read data output is synchronized with this clock. read data output at the rising edge of the rck cycle when /oe is pulled low (enabled). the internal read address pointer is incremented with this clo ck input. /we write enable input: /we controls the enabling/disabling of the data input. when /we is pulled low, input data is acquired at the rising edge of the wck cycle. when /we is pulled high, the 384k x8 memory cell array sram cache timing generator & arbiter write address counter read address counter refresh address counter di7~ di0 do7~ do0 /oe rck /rrst /re wck /wrst /we AL422-03 block diagram input buffer write data register read data register output buffer
AL422 AL422b january 23, 2001 14 memory does not accept data input. the write addre ss pointer is stopped at the current position. /we signal is fetched at the rising edge of the wck cycle. /re read enable input: /re controls the operation of the data output. when /re is pulled low, output data is provided at the rising edge of the rck cycle and the internal read address is incremented automatically. /re signal is fetched at the rising edge of the rck cycle. /oe output enable input: / oe controls the enabling/disabling of the data output. when /oe is pulled low, output data is provided at the rising edge of the rck cycle. when /oe is pulled high, data output is disabled and the output pins remain at high impedance status. /oe signal is fetched at the rising edge of rck cycle. /wrst write reset input: this reset signal initializes the write address to 0, and is fetched at the rising edge of the wck input cycle. /rrst write reset input: this reset signal initializes the read address to 0, and is fetched at the rising edge of the rck input cycle. tst test pin: for testing purpose only. it should be pulled low for normal applications. dec: decoupling cap pin, should be connected to a 1 m f or 2.2 m f capacitor to ground for 5v application. for 3.3v application, the dec pin can be simply connected to the 3.3v power with regular 0.1 m f bypass c apacitor. 8.1 memory operation initialization apply /wrst and /rrst 0.1ms after power on, then follow the following instructions for normal operation. reset operation the reset signal can be given at any time regardless of the /we, /re and /oe status, ho wever, they still need to meet the setup time and hold time requirements with reference to the clock input. when the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are enabled again. when /wrst signal is pulled low, the data input address will be set to 0 and the data in the input buffer will be flushed into memory cell array. when /rrst signal is pulled low, the data output address will be set to 0 and pre - fetch the data from memory cell array to output buffer.
AL422 AL422b january 23, 2001 15 write operation data input di7~di0 is written into the write register at the wck input when /we is pulled low. the write data should meet the setup time and hold time requirements with reference to the wck input cycle. write operation is prohib ited when /we is pulled high, and the write address pointer is stopped at the current position. the write address starts from there when the /we is pulled low again. the /we signal needs to meet the setup time and hold time requirements with reference to the wck input cycle. read operation data output do7~do0 is written into the read register at the rck input when both /re and /oe are pulled low. the output data is ready after t ac (access time) from the rising edge of the rck input cycle. the read addres s pointer is stopped at the current position when /re is pulled high, and starts there when /re is pulled low again. /oe needs to be pulled low for read operations. when /oe is pulled high, the data outputs will be at high impedance stage. the read addre ss pointer still increases synchronously with rck regardless of the /oe status. the /re and /oe signals need to meet the setup time and hold time requirements with reference to the rck input cycle. when the new data is read, the read address should be bet ween 128 to 393,247 cycles after the write address, otherwise the output may not be new data. 8.2 5v and 3.3v applications the AL422 can accept either 3.3v or 5v power with slightly different external configuration. the internal voltage regulator can co nvert 5v power to 3.3v for the embedded dram and logic circuitry when 5v power is applied to vdd pin (#10) only and leave the dec pin (#19) decoupled by a capacitor of 1 m f or 2.2 m f to ground. the regulator can also be bypassed when 3.3v power is applied t o both vdd and dec pins. in either case the AL422 is 5v or 3.3v i/o tolerant. the 3.3v configuration consumes less power and is free from noise interference from the voltage regulator so may be more ideal for high - speed applications. please note that usi ng the AL422b with 5v configuration can directly replace the previous AL422v5; using it with 3.3v configuration can directly replace the previous AL422v3. no additional modification is required.
AL422 AL422b january 23, 2001 16 the 5v configuration (direct replacement of the previous al4 22v5) is as follows: the 3.3v configuration (direct replacement of the previous AL422v3) is as follows: 8.3 application notes 8.3.1 irregular read/write it is recommended that the wck and rck are kept running at least 1mhz at all times. the faster one of wck and rck is used as the dram refresh timing clock and has to be kept free running. when irregular fifo i/o control is needed, keep the clock free running and use /we or /re to control the i/o as follows: the following drawing shows irregular clo ck and should be avoided: vdd dec 5v AL422b 0.1uf 2.2uf vdd dec 3.3v AL422b 3.3v 0.1uf 0.1uf 10 19 data /we AL422-17 slow write - correct wck
AL422 AL422b january 23, 2001 17 8.3.2 the proper manipulation of fifo access the fifo memory is designed to allow easy field delay, time - base conversion, and other types of signal processing. to ensure the expectant data can be read out from the AL422 fifo , the proper manipulation on the AL422 fifo memory is highly recommended 1. the read address should be between 128 to 393,247 cycles after the write address to read the current field data. (the restriction is indicated in the ?read operation? section). 2. the proper fifo access must make sure after read reset, the read operation will either read all the old data (last field data) until next read reset, or follow the constraint 1 above to read newly update data. in any 2 read resets interval, the fifo ac cess can not read old data (the field data are written before last write reset), and stop for a period then read the newly update data (even at that time, write counter is ahead of read counter by more than 128 cycles). if the fifo memory manipulations v iolate the above conditions, some amount of consecutive unexpected data (old data) will be read at the fifo data bus. 8.3.3 single field write with multiple read operation it is one of the functions for fifo memory that can buffer a field data and do mult iple times of fields read access. in some applications, such as still image capturing, require one field write and multiple field data read operations. in order not to violate the 128 cycles of write to read delay latency rule, the write address (pointer ) needs to be reset to 0 for the coming multiple read operations so that fifo can provide the expectant data at do bus. 8.3.4 one field delay line (the old data read) as the design shown in diagram by applying the reset every 1 - field cycle (with the commo n signal for /wrst and /rrst) and a constant read/write operation (with all /we, /re and /oe are tied to ground), ?1 field delay line? timing is shown in timing chart below. when the difference between the data /we AL422-16 slow write - incorrect wck
AL422 AL422b january 23, 2001 18 write address and the read address is 0 (the read address and the write address are the same), the old field data are read as shown in the timing chart. AL422 1 field delay line diagram 8-bit input 8-bit output di[7:0] AL422 /we wck do[7:0] /re rck reset clock /oe /rrst /wrst rck wck /rrst /wrst di7~0 0 AL422-08 1 field delay line timing diagram 1 n cycle 0 cycle 1 cycle n do7~0 0 0 field m field m + 1 1 1 cycle 0 t ac data of field m cycle 1
AL422 AL422b january 23, 2001 19 9.0 mechanical drawing 28 pin plastic sop:
contact information averlogic technologies, inc. 6840 via del oro suite 160 san jose, ca 95119 usa tel : 1 408 361 - 0400 fax : 1 408 361 - 0404 e - mail : sales@averlogic.com url : www.averlogic.com

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